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14.4. Cross trigger register summary

This section describes the cross trigger registers in the Cortex-A53 processor. These registers are accessed through the internal memory-mapped interface or the external debug interface.

Table 14.3 gives a summary of the Cortex-A53 cross trigger registers. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Table 14.3. Cross trigger register summary
OffsetNameTypeDescription
0x000CTICONTROLRWCTI Control Register
0x000-0x00C--Reserved
0x010CTIINTACKWOCTI Output Trigger Acknowledge Register
0x014CTIAPPSETRWCTI Application Trigger Set Register
0x018CTIAPPCLEARWOCTI Application Trigger Clear Register
0x01CCTIAPPPULSEWOCTI Application Pulse Register
0x020CTIINEN0RWCTI Input Trigger to Output Channel Enable Registers
0x024CTIINEN1RW
0x028CTIINEN2RW
0x02CCTIINEN3RW
0x030CTIINEN4RW
0x034CTIINEN5RW
0x038CTIINEN6RW
0x03CCTIINEN7RW
0x040-0x09C--Reserved
0x0A0CTIOUTEN0RWCTI Input Channel to Output Trigger Enable Registers
0x0A4CTIOUTEN1RW
0x0A8CTIOUTEN2RW
0x0ACCTIOUTEN3RW
0x0B0CTIOUTEN4RW
0x0B4CTIOUTEN5RW
0x0B8CTIOUTEN6RW
0x0BCCTIOUTEN7RW
0x0C0-0x12C--Reserved
0x130CTITRIGINSTATUSROCTI Trigger In Status Register
0x134CTITRIGOUTSTATUSROCTI Trigger Out Status Register
0x138CTICHINSTATUSROCTI Channel In Status Register
0x13CCTICHOUTSTATUSROCTI Channel Out Status Register
0x140CTIGATERWCTI Channel Gate Enable Register
0x144ASICCTLRWCTI External Multiplexer Control Register
0x148-0xF7C--Reserved
0xF00CTIITCTRLRWCTI Integration Mode Control Register
0xF04-0xFA4--Reserved
0xFA0CTICLAIMSETRWCTI Claim Tag Set Register
0xFA4CTICLAIMCLRRWCTI Claim Tag Clear Register
0xFA8CTIDEVAFF0ROCTI Device Affinity Register 0
0xFACCTIDEVAFF1ROCTI Device Affinity Register 1
0xFB0CTILARWOCTI Lock Access Register
0xFB4CTILSRROCTI Lock Status Register
0xFB8CTIAUTHSTATUSROCTI Authentication Status Register
0xFBCCTIDEVARCHROCTI Device Architecture Register
0xFC0CTIDEVID2ROCTI Device ID Register 2
0xFC4CTIDEVID1ROCTI Device ID Register 1
0xFC8CTIDEVIDROCTI Device Identification Register
0xFCCCTIDEVTYPEROCTI Device Type Register
0xFD0CTIPIDR4ROPeripheral Identification Register 4
0xFD4CTIPIDR5ROPeripheral Identification Register 5-7
0xFD8CTIPIDR6RO
0xFDCCTIPIDR7RO
0xFE0CTIPIDR0ROPeripheral Identification Register 0
0xFE4CTIPIDR1ROPeripheral Identification Register 1
0xFE8CTIPIDR2ROPeripheral Identification Register 2
0xFECCTIPIDR3ROPeripheral Identification Register 3
0xFF0CTICIDR0ROComponent Identification Register 0
0xFF4CTICIDR1ROComponent Identification Register 1
0xFF8CTICIDR2ROComponent Identification Register 2
0xFFCCTICIDR3ROComponent Identification Register 3

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