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11.5. AArch32 debug register summary

Table 11.7 summarizes the 32-bit and 64-bit debug control registers that are accessible in the AArch32 Execution state from the internal CP14 interface. These registers are accessed by the MCR and MRC instructions in the order of CRn, op2, CRm, Op1 or MCRR and MRRC instructions in the order of CRm, Op1. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

See the Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped and the external debug interface.

Table 11.7. AArch32 debug register summary
OffsetCRnOp2CRmOp1NameTypeDescription
-c00c00DBGDIDRRODebug ID Register
-c00c10DBGDSCRintRODebug Status and Control Register, Internal View
-c00c20DBGDCCINTRWDebug Comms Channel Interrupt Enable Register
0x08Cc00c50DBGDTRTXintWODebug Data Transfer Register, Transmit, Internal View
     DBGDTRRXintRODebug Data Transfer Register, Receive, Internal View
-c00c60DBGWFAR[a]RWWatchpoint Fault Address Register, res0
-c00c70DBGVCRRWDebug Vector Catch Register
-c02c00DBGDTRRXextRWDebug Data Transfer Register, Receive, External View
-c02c20DBGDSCRextRWDebug Status and Control Register, External View
-c02c30DBGDTRTXextRWDebug Data Transfer Register, Transmit, External View
0x098c02c60DBGOSECCRRWDebug OS Lock Exception Catch Control Register
0x400c04c00DBGBVR0RWDebug Breakpoint Value Register 0
0x410c04c10DBGBVR1RWDebug Breakpoint Value Register 1
0x420c04c20DBGBVR2RWDebug Breakpoint Value Register 2
0x430c04c30DBGBVR3RWDebug Breakpoint Value Register 3
0x440c04c40DBGBVR4RWDebug Breakpoint Value Register 4
0x450c04c50DBGBVR5RWDebug Breakpoint Value Register 5
0x408c05c00DBGBCR0RWDebug Breakpoint Control Registers, EL1
0x418c05c10DBGBCR1RWDebug Breakpoint Control Registers, EL1
0x428c05c20DBGBCR2RWDebug Breakpoint Control Registers, EL1
0x438c05c30DBGBCR3RWDebug Breakpoint Control Registers, EL1
0x448c05c40DBGBCR4RWDebug Breakpoint Control Registers, EL1
0x458c05c50DBGBCR5RWDebug Breakpoint Control Registers, EL1
0x800c06c00DBGWVR0RWDebug Watchpoint Value Register 0
0x810c06c10DBGWVR1RWDebug Watchpoint Value Register 1
0x820c06c20DBGWVR2RWDebug Watchpoint Value Register 2
0x830c06c30DBGWVR3RWDebug Watchpoint Value Register 3
0x808c07c00DBGWCR0RWDebug Watchpoint Control Registers, EL1
0x818c07c10DBGWCR1RWDebug Watchpoint Control Registers, EL1
0x828c07c20DBGWCR2RWDebug Watchpoint Control Registers, EL1
0x838c07c30DBGWCR3RWDebug Watchpoint Control Registers, EL1
-c10c00DBGDRAR[31:0]RO Debug ROM Address Register
---c1-DBGDRAR[63:0]RO
0x444c11c40DBGBXVR4RWDebug Breakpoint Extended Value Register 4
0x454c11c50DBGBXVR5RWDebug Breakpoint Extended Value Register 5
0x300c14c00DBGOSLARWODebug OS Lock Access Register
-c14c10DBGOSLSRRODebug OS Lock Status Register
-c14c30DBGOSDLRRWDebug OS Double Lock Register
0x310c14c40DBGPRCRRWDebug Power/Reset Control Register
-c22c00DBGDSAR[31:0][b]RODebug Self Address Register res0
--0c2-DBGDSAR[63:0][b]RO
-c77c00DBGDEVID2RODebug Device ID Register 2, res0
-c77c10DBGDEVID1RODebug Device ID Register 1
-c77c20DBGDEVIDRO Debug Device ID Register
0xFA0c76c80DBGCLAIMSETRWDebug Claim Tag Set Register
0xFA4c76c90DBGCLAIMCLRRWDebug Claim Tag Clear Register
0xFB8c76c140DBGAUTHSTATUSRODebug Authentication Status Register

[a] Previously returned information about the address of the instruction that accessed a watchpoint address. This register is now deprecated and is res0.

[b] Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the processor. This register is now deprecated and res0.


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