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11.3. AArch64 debug register summary

Table 11.3 summarizes debug control registers that are accessible in the AArch64 Execution state. These registers are accessed by the MRS and MSR instructions in the order of Op0, CRn, Op1, CRm, Op2.

See the Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped or the external debug interface. The 64-bit registers cover two addresses on the external memory interface. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Table 11.3. AArch64 debug register summary
OSDTRRX_EL1RW-32Debug Data Transfer Register, Receive, External View
DBGBVR0_EL1RW-64Debug Breakpoint Value Register 0
DBGBCR0_EL1RW-32Debug Breakpoint Control Registers, EL1
DBGWVR0_EL1RW-64Debug Watchpoint Value Register 0
DBGWCR0_EL1RW-32Debug Watchpoint Control Registers, EL1
DBGBVR1_EL1RW-64Debug Breakpoint Value Register 1
DBGBCR1_EL1RW-32Debug Breakpoint Control Registers, EL1
DBGWVR1_EL1RW-64Debug Watchpoint Value Register 1
DBGWCR1_EL1RW-32Debug Watchpoint Control Registers, EL1
MDCCINT_EL1RW0x0000000032Monitor Debug Comms Channel Interrupt Enable Register
MDSCR_EL1RW-32Monitor Debug System Register
DBGBVR2_EL1RW-64Debug Breakpoint Value Register 2
DBGBCR2_EL1RW-32Debug Breakpoint Control Registers, EL1
DBGWVR2_EL1RW-64Debug Watchpoint Value Register 2
DBGWCR2_EL1RW-32Debug Watchpoint Control Registers, EL1
OSDTRTX_EL1RW-32Debug Data Transfer Register, Transmit, External View
DBGBVR3_EL1RW-64Debug Breakpoint Value Register 3
DBGBCR3_EL1RW-32Debug Breakpoint Control Registers, EL1
DBGWVR3_EL1RW-64Debug Watchpoint Value Register 3
DBGWCR3_EL1RW-32 Debug Watchpoint Control Registers, EL1
DBGBVR4_EL1RW-64Debug Breakpoint Value Register 4
DBGBCR4_EL1RW-32Debug Breakpoint Control Registers, EL1
DBGBVR5_EL1RW-64Debug Breakpoint Value Register 5
DBGBCR5_EL1RW-32Debug Breakpoint Control Registers, EL1
OSECCR_EL1RW-32Debug OS Lock Exception Catch Register
MDCCSR_EL0RO-32Monitor Debug Comms Channel Status Register
DBGDTR_EL0RW-64Debug Data Transfer Register, half-duplex
DBGDTRTX_EL0WO-32Debug Data Transfer Register, Transmit, Internal View
DBGDTRRX_EL0RO-32Debug Data Transfer Register, Receive, Internal View
DBGVCR32_EL2RW-32Debug Vector Catch Register
MDRAR_EL1RO[a]64Debug ROM Address Register
OSLAR_EL1WO-32Debug OS Lock Access Register
OSLSR_EL1RO0x0000000A32Debug OS Lock Status Register
OSDLR_EL1RW0x0000000032Debug OS Double Lock Register
DBGPRCR_EL1RW-32Debug Power/Reset Control Register
DBGCLAIMSET_EL1RW0x000000FF32Debug Claim Tag Set Register
DBGCLAIMCLR_EL1RW0x0000000032Debug Claim Tag Clear Register
DBGAUTHSTATUS_EL1RO-32Debug Authentication Status Register

[a] Resets to the physical address of the ROM table +3.

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