The TRCDEVAFF0 characteristics are:
Provides an additional core identification mechanism for scheduling purposes in a cluster.
TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
The TRCDEVAFF0 is:
Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register. See Multiprocessor Affinity Register.
Architecturally mapped to external TRCDEVAFF0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
TRCDEVAFF0 is a 32-bit register.
Figure 13.58 shows the TRCDEVAFF0 bit assignments.
Table 13.59 shows the TRCDEVAFF0 bit assignments.
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A53 processor. The possible values are:
To access the TRCDEVAFF0:
MRC p15,0,<Rt>,c0,c0,5 ; Read TRCDEVAFF0 into Rt
Register access is encoded as follows:
The TRCDEVAFF0 can be accessed through the internal memory-mapped
interface and the external debug interface, offset