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13.8.57. Device Affinity Register 1

The TRCDEVAFF1 characteristics are:


The value is a read-only copy of MPIDR_EL1[63:32] as seen from EL3, unaffected by VMPIDR_EL2.

Usage constraints

Accessible only from the memory-mapped interface or the external debugger interface.


Available in all configurations.


TRCDEVAFF1 is a 32-bit RO management register.

For the Cortex-A53 processor, MPIDR_EL1[63:32] is res0.

See the register summary in Table 13.3.

The TRCDEVAFF1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFAC.