The TRCIDR3 characteristics are:
Whether TRCVICTLR is supported.
The number of cores available for tracing.
If an exception level supports instruction tracing.
The minimum threshold value for instruction trace cycle counting.
Whether the synchronization period is fixed.
Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the processor.
- Usage constraints
There are no usage constraints.
Available in all configurations.
See the register summary in Table 13.3.
Figure 13.36 shows the TRCIDR3 bit assignments.
Table 13.37 shows the TRCIDR3 bit assignments.
Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
Indicates the number of cores available for tracing:
Indicates whether stall control is implemented:
Indicates whether TRCSTALLCTLR is implemented:
This field is used in conjunction with SYSSTALL.
Indicates whether there is a fixed synchronization period:
Indicates whether TRCVICTLR.TRCERR is implemented:
Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding exception level:
Each bit controls whether instruction tracing in Secure state is implemented for the corresponding exception level:
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:
The TRCIDR3 can be accessed through the internal memory-mapped
interface and the external debug interface, offset