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13.8.39. Single-Shot Comparator Status Register 0

The TRCSSCSR0 characteristics are:


Indicates the status of the single-shot comparator:

  • TRCSSCSR0 is sensitive to instruction addresses.

Usage constraints
  • Accepts writes only when the trace unit is disabled.

  • The STATUS bit value is stable only when TRCSTATR.PMSTABLE==1.


Available in all configurations.


See the register summary in Table 13.3.

Figure 13.41 shows the TRCSSCSR0 bit assignments.

Figure 13.41. TRCSSCSR0 bit assignments

Figure 13.41. TRCSSCSR0 bit assignments

Table 13.42 shows the TRCSSCSR0 bit assignments.

Table 13.42. TRCSSCSR0 bit assignments

Single-shot status. This indicates whether any of the selected comparators have matched:


Match has not occurred.


Match has occurred at least once.

When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

[30:3]-Reserved, res0.

Data value comparator support:


Single-shot data value comparisons not supported.


Data address comparator support:


Single-shot data address comparisons not supported.


Instruction address comparator support:


Single-shot instruction address comparisons supported.

The TRCSSCSR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x2A0.