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13.8.8. Stall Control Register

The TRCSTALLCTLR characteristics are:


Enables the ETM trace unit to stall the Cortex-A53 processor if the ETM trace unit FIFO overflows.

Usage constraints
  • You must always program this register as part of trace unit initialization.

  • Accepts writes only when the trace unit is disabled.


Available in all configurations.


See the register summary in Table 13.3.

Figure 13.10 shows the TRCSTALLCTLR bit assignments.

Figure 13.10. TRCSTALLCTLR bit assignments

Figure 13.10. TRCSTALLCTLR bit assignments

Table 13.11 shows the TRCSTALLCTLR bit assignments.

Table 13.11. TRCSTALLCTLR bit assignments
[31:9]-Reserved, res0.

Instruction stall bit. Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL:


The trace unit does not stall the processor.


The trace unit can stall the processor.

[7:4]-Reserved, res0.

Threshold level field. The field can support 4 monotonic levels from 0b00 to 0b11, where:


Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.


Maximum invasion occurs but there is less risk of a FIFO overflow.

[1:0]-Reserved, res0.

The TRCSTALLCTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x02c.