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10.2. Generic Timer functional description

The Cortex-A53 processor provides a set of timer registers within each core of the cluster. The timers are:

  • An EL1 Non-secure physical timer.

  • An EL1 Secure physical timer.

  • An EL2 physical timer.

  • A virtual timer.

The Cortex-A53 processor does not include the system counter. This resides in the SoC. The system counter value is distributed to the Cortex-A53 processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0].

Because CNTVALUEB is generated from a system counter that typically operates at a slower frequency than the main processor CLKIN, the CNTCLKEN input is provided as a clock enable for the CNTVALUEB bus. CNTCLKEN is registered inside the Cortex-A53 processor before being used as a clock enable for the CNTVALUEB[63:0] registers. This allows a multicycle path to be applied to the CNTVALUEB[63:0] bus. Figure 10.1 shows the interface.

Figure 10.1. Architectural counter interface

Figure 10.1. Architectural counter interface

The value on the CNTVALUEB[63:0] bus is required to be stable whenever the internally registered version of the CNTCLKEN clock enable is asserted. CNTCLKEN must be synchronous and balanced with CLK and must toggle at integer ratios of the processor CLK.

See Clocks for more information about CNTCLKEN.

Each timer provides an active-LOW interrupt output to the SoC.

Table 10.1 shows the signals that are the external interrupt output pins.

Table 10.1. Generic Timer signals
nCNTPNSIRQ[n:0]EL1 Non-secure physical timer event
nCNTPSIRQ[n:0]EL1 Secure physical timer event
nCNTHPIRQ[n:0]EL2 physical timer event
nCNTVIRQ[n:0]Virtual timer event

[a] n is the number of cores present in the cluster, minus one.

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