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1.5. Implementation options

Table 1.1 lists the implementation options at build time for the Cortex-A53 processor.

Table 1.1. Cortex-A53 processor implementation options
FeatureRange of options
Number of cores

Up to four cores.

L1 Instruction cache size
  • 8K.

  • 16K.

  • 32K.

  • 64K.

L1 Data cache size
  • 8K.

  • 16K.

  • 32K.

  • 64K.

L2 cacheIncluded or not.
 L2 cache size
  • 128K.

  • 256K.

  • 512K.

  • 1024K.

  • 2048K.

 L2 data RAM input latency
  • 1 cycle.

  • 2 cycles.

 L2 data RAM output latency
  • 2 cycles.

  • 3 cycles.

 SCU-L2 cache protectionIncluded or not.
Advanced SIMD and Floating-point ExtensionIncluded or not.
Cryptography ExtensionIncluded or not.
CPU cache protection[a]Included or not.
AMBA 5 CHI or AMBA 4 ACE interface
  • AMBA 5 CHI.

  • AMBA 4 ACE.

Accelerator Coherency Port (ACP)[b]Included or not.
v7 or v8 Debug memory map
  • v8 Debug memory map.

  • v7 Debug memory map.

[a] Not implemented if the L2 cache is implemented and SCU-L2 cache protection is not implemented.

[b] Not implemented if the Cortex-A53 processor does not include an L2 cache.


Note

  • The L1 duplicate tags in the SCU are protected by the CPU cache protection.

  • There is no option to implement floating-point without Advanced SIMD.

  • There is no option to implement the Cryptography Extension without the Advanced SIMD and Floating-point Extension.

  • All cores share a common L2 cache.

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