The ARMv8-A architecture provides for multiple maps from the VA space, that are translated differently. The TLB entries store all the required context information to facilitate a match and avoid the requirement for a TLB flush on a context or virtual machine switch. Each TLB entry contains a VA, block size, PA, and a set of memory properties that include the memory type and access permissions. Each entry is associated with a particular ASID, or is global for all application spaces. The TLB entry also contains a field to store the VMID in the entry, applicable to accesses made from the Non-secure EL0 and EL1 exception levels. There is also a memory space identifier that records whether the request occurred at the:
EL3 exception level, if EL3 is AArch64.
Non-secure EL2 exception level.
Secure and Non-secure EL0 or EL1 exception levels and EL3 exception level when EL3 is AArch32.
A TLB entry match occurs when the following conditions are met:
Its VA, moderated by the page size such as the VA bits[47:N], where N is log2 of the block size for that translation stored in the TLB entry, matches that of the requested address.
The memory space matches the memory space state of the requests. The memory space can be one of four values:
Secure EL3, when EL3 is AArch64.
Secure EL0 or EL1, and EL3 when EL3 is AArch32.
Non-secure EL0 or EL1.
The ASID matches the current ASID held in the CONTEXTIDR, TTBR0, or TTBR1 register or the entry is marked global.
The VMID matches the current VMID held in the VTTBR register.
For a request originating from EL2 or AArch64 EL3, the ASID and VMID match are ignored.
For a request not originating from Non-secure EL0 or EL1, the VMID match is ignored.