The CTR_EL0 characteristics are:
Provides information about the architecture of the caches.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
CTR is architecturally mapped to AArch64 register CTR_EL0. See Cache Type Register.
There is one copy of this register that is used in both Secure and Non-secure states.
CTR is a 32-bit register.
Figure 4.95 shows the CTR bit assignments.
Table 4.59 shows the CTR bit assignments.
Cache Write-Back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls:
L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls.
To access the CTR:
MRC p15,0,<Rt>,c0,c0,1 ; Read CTR into Rt
Register access is encoded as follows: