The HVBAR characteristics are:
Holds the exception base address for any exception that is taken to Hyp mode.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW -
The HVBAR is:
Architecturally mapped to the AArch64 VBAR_EL2[31:0]. See Vector Base Address Register, EL2.
HVBAR is a 32-bit register.
Figure 4.138 shows the HVBAR bit assignments.
Table 4.242 shows the HVBAR bit assignments.
|[31:5]||Vector Base Address||Bits[31:5] of the base address of the exception vectors, for exceptions taken in this exception level. Bits[4:0] of an exception vector are the exception offset.|
To access the HVBAR:
MRC p15, 4, <Rt>, c12, c0, 0 ; Read HVBAR into Rt MCR p15, 4, <Rt>, c12, c0, 0 ; Write Rt to HVBAR