The ID_ISAR3 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR4, and ID_ISAR5. See:
ID_ISAR3 is architecturally mapped to AArch64 register ID_ISAR3_EL1. See AArch32 Instruction Set Attribute Register 3.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR3 is a 32-bit register.
Figure 4.89 shows the ID_ISAR3 bit assignments.
Table 4.174 shows the ID_ISAR3 bit assignments.
Indicates the implemented Thumb Execution Environment (T32EE) instructions:
Indicates support for True NOP instructions:
Indicates the support for T32 non flag-setting
Indicates the implemented Table Branch instructions in the T32 instruction set.
Indicates the implemented Synchronization Primitive instructions.
Indicates the implemented SVC instructions:
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
Indicates the implemented Saturate instructions:
To access the ID_ISAR3:
MRC p15, 0, <Rt>, c0, c2, 3 ; Read ID_ISAR3 into Rt
Register access is encoded as follows: