The ID_ISAR4 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5. See:
ID_ISAR4 is architecturally mapped to AArch64 register ID_ISAR4_EL1. See AArch32 Instruction Set Attribute Register 4.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR4 is a 32-bit register.
Figure 4.90 shows the ID_ISAR4 bit assignments.
Table 4.176 shows the ID_ISAR4 bit assignments.
Indicates support for the memory system
locking the bus for
Indicates the implemented M profile instructions to modify the PSRs:
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions:
Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
Indicates the implemented
Indicates the support for writeback addressing modes:
Indicates the support for instructions with shifts:
Indicates the implemented unprivileged instructions:
To access the ID_ISAR4:
MRC p15, 0, <Rt>, c0, c2, 4 ; Read ID_ISAR4 into Rt
Register access is encoded as follows: