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4.5.11. Memory Model Feature Register 1

The ID_MMFR1 characteristics are:

Purpose

Provides information about the memory model and memory management support in AArch32.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

Must be interpreted with ID_MMFR0, ID_MMFR2, and ID_MMFR3. See:

Configurations

ID_MMFR1 is architecturally mapped to AArch64 register ID_MMFR1_EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_MMFR1 is a 32-bit register.

Figure 4.83 shows the ID_MMFR1 bit assignments.

Figure 4.83. ID_MMFR1 bit assignments

Figure 4.83. ID_MMFR1 bit assignments

Table 4.162 shows the ID_MMFR1 bit assignments.

Table 4.162. ID_MMFR1 bit assignments
BitsNameFunction
[31:28]BPred

Indicates branch predictor management requirements:

0x4

For execution correctness, branch predictor requires no flushing at any time.

[27:24]L1TstCln

Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache implementation:

0x0

None supported.

[23:20]L1Uni

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:

0x0

None supported.

[19:16]L1Hvd

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:

0x0

None supported.

[15:12]L1UniSW

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:

0x0

None supported.

[11:8]L1HvdSW

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation:

0x0

None supported.

[7:4]L1UniVA

Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:

0x0

None supported.

[3:0]L1HvdVA

Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:

0x0

None supported.


To access the ID_MMFR1:

MRC p15, 0, <Rt>, c0, c1, 5; Read ID_MMFR1 into Rt

Register access is encoded as follows:

Table 4.163. ID_MMFR1 access encoding
coprocopc1CRnCRmopc2
111100000000001101