The ID_ISAR0_EL1 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_ISAR0_EL1 is architecturally mapped to AArch32 register ID_ISAR0. See Instruction Set Attribute Register 0.
ID_ISAR0_EL1 is a 32-bit register.
Figure 4.11 shows the ID_ISAR0_EL1 bit assignments.
Table 4.33 shows the ID_ISAR0_EL1 bit assignments.
Indicates the implemented Divide instructions:
Indicates the implemented Debug instructions:
Indicates the implemented Coprocessor instructions:
Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:
Indicates the implemented bit field instructions:
Indicates the implemented Bit Counting instructions:
Indicates the implemented Swap instructions in the A32 instruction set:
To access the ID_ISAR0_EL1:
MRS <Xt>, ID_ISAR0_EL1 ; Read ID_ISAR0_EL1 into Xt
Register access is encoded as follows: