The ID_ISAR4_EL1 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_ISAR4_EL1 is architecturally mapped to AArch32 register ID_ISAR4. See Instruction Set Attribute Register 4.
ID_ISAR4_EL1 is a 32-bit register.
Figure 4.15 shows the ID_ISAR4_EL1 bit assignments.
Table 4.41 shows the ID_ISAR4_EL1 bit assignments.
Indicates support for the memory system
locking the bus for
Indicates the implemented M profile instructions to modify the PSRs:
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions:
Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
Indicates the implemented
Indicates the support for Write-Back addressing modes:
Indicates the support for instructions with shifts.
Indicates the implemented unprivileged instructions.
To access the ID_ISAR4_EL1:
MRS <Xt>, ID_ISAR4_EL1 ; Read ID_ISAR4_EL1 into Xt
Register access is encoded as follows: