The ID_MMFR0_EL1 characteristics are:
Provides information about the memory model and memory management support in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_MMFR0_EL1 is architecturally mapped to AArch32 register ID_MMFR0. See Memory Model Feature Register 0.
ID_MMFR0_EL1 is a 32-bit register.
Figure 4.7 shows the ID_MMFR0_EL1 bit assignments.
Table 4.25 shows the ID_MMFR0_EL1 bit assignments.
Indicates the innermost shareability domain implemented:
Indicates support for Fast Context Switch Extension (FCSE):
Indicates support for Auxiliary registers:
Indicates support for TCMs and associated DMAs:
Indicates the number of shareability levels implemented:
Indicates the outermost shareability domain implemented:
Indicates support for a Protected Memory System Architecture (PMSA):
Indicates support for a Virtual Memory System Architecture (VMSA).
To access the ID_MMFR0_EL1:
MRS <Xt>, ID_MMFR0_EL1 ; Read ID_MMFR0_EL1 into Xt
Register access is encoded as follows: