The ID_MMFR3_EL1 characteristics are:
Provides information about the memory model and memory management support in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_MMFR3_EL1 is architecturally mapped to AArch32 register ID_MMFR3. See Memory Model Feature Register 3.
ID_MMFR3_EL1 is a 32-bit register.
Figure 4.10 shows the ID_MMFR3_EL1 bit assignments.
Table 4.31 shows the ID_MMFR3_EL1 bit assignments.
Supersections. Indicates support for supersections:
Cached memory size. Indicates the size of physical memory supported by the processor caches:
Coherent walk. Indicates whether translation table updates require a clean to the point of unification:
Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are broadcast:
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.
Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.
[a] Invalidate data cache by MVA operations are treated as clean and invalidate data cache by MVA operations on the executing core. If the operation is broadcast to another core then it is broadcast as an invalidate data cache by MVA operation.
To access the ID_MMFR3_EL1:
MRS <Xt>, ID_MMFR3_EL1 ; Read ID_MMFR3_EL1 into Xt
Register access is encoded as follows: