The ID_AA64MMFR0_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in the AArch64 Execution state.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_AA64MMFR0_EL1 is architecturally mapped to external register ID_AA64MMFR0_EL1.
ID_AA64MMFR0_EL1 is a 64-bit register.
Figure 4.20 shows the ID_AA64MMFR0_EL1 bit assignments.
Table 4.51 shows the ID_AA64MMFR0_EL1 bit assignments.
Support for 4 KB memory translation granule size:
Support for 64 KB memory translation granule size:
Support for 16 KB memory translation granule size:
Mixed-endian support only at EL0.
Secure versus Non-secure Memory distinction:
Mixed-endian configuration support:
Number of ASID bits:
Physical address range supported:
To access the ID_AA64MMFR0_EL1:
MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt
Register access is encoded as follows: