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4.3.57. Exception Syndrome Register, EL1

The ESR_EL1 characteristics are:

Purpose

Holds syndrome information for an exception taken to EL1.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RWRWRWRWRW
Configurations

ESR_EL1 is architecturally mapped to AArch32 register DFSR (NS). See Data Fault Status Register.

Attributes

ESR_EL1 is a 32-bit register.

Figure 4.50 shows the ESR_EL1 bit assignments.

Figure 4.50. ESR_EL1 bit assignments

Figure 4.50. ESR_EL1 bit assignments

Table 4.89 shows the ESR_EL1 bit assignments.

Table 4.89.  ESR_EL1 bit assignments
BitsNameFunction
[31:26]ECException Class. Indicates the reason for the exception that this register holds information about.
[25]IL

Instruction Length for synchronous exceptions. The possible values are:

0

16-bit.

1

32-bit.

This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer misalignment, data aborts for which the ISV bit is 0, exceptions caused by an illegal instruction set state, and exceptions using the 0x00 Exception Class.

[24]ISS Valid

Syndrome valid. The possible values are:

0

ISS not valid, ISS is res0.

1

ISS valid.

[23:0]ISS

Syndrome information.


To access the ESR_EL1:

MRS <Xt>, ESR_EL1 ; Read EL1 Exception Syndrome Register
MSR ESR_EL1, <Xt> ; Write EL1 Exception Syndrome Register
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