The ISR_EL1 characteristics are:
Shows whether an IRQ, FIQ, or external abort is pending. An indicated pending abort might be a physical abort or a virtual abort.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ISR_EL1 is architecturally mapped to AArch32 register ISR. See Interrupt Status Register.
ISR_EL1 is a 32-bit register.
Figure 4.70 shows the ISR_EL1 bit assignments.
Table 4.114 shows the ISR_EL1 bit assignments.
External abort pending bit:
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
FIQ pending bit. Indicates whether an FIQ interrupt is pending:
To access the ISR_EL1:
MRS <Xt>, ISR_EL1 ; Read ISR_EL1 into Xt
Register access is encoded as follows: