You copied the Doc URL to your clipboard.

4.3.1. Main ID Register, EL1

The MIDR_EL1 characteristics are:

Purpose

Provides identification information for the processor, including an implementer code for the device and a device ID number.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

The MIDR_EL1 is:

  • Architecturally mapped to the AArch32 MIDR register. See Main ID Register.

  • Architecturally mapped to external MIDR_EL1 register.

Attributes

MIDR_EL1 is a 32-bit register.

Figure 4.1 shows the MIDR_EL1 bit assignments.

Figure 4.1. MIDR_EL1 bit assignments

Figure 4.1. MIDR_EL1 bit assignments

Table 4.13 shows the MIDR_EL1 bit assignments.

Table 4.13. MIDR_EL1 bit assignments
BitsNameFunction
[31:24]Implementer

Indicates the implementer code. This value is:

0x41

ASCII character 'A' - implementer is ARM.

[23:20]Variant

Indicates the variant number of the processor. This is the major revision number x in the rx part of the rxpy description of the product revision status. This value is:

0x0

r0p2.

[19:16]Architecture

Indicates the architecture code. This value is:

0xF

Defined by CPUID scheme.

[15:4]PartNum

Indicates the primary part number. This value is:

0xD03

Cortex-A53 processor.

[3:0]Revision

Indicates the minor revision number of the processor. This is the minor revision number y in the py part of the rxpy description of the product revision status. This value is:

0x2

r0p2.


To access the MIDR_EL1:

MRS <Xt>, MIDR_EL1 ; Read MIDR_EL1 into Xt

Table 4.14 shows the register access encoding:

Table 4.14. MIDR_EL1 access encoding
op0op1CRnCRmop2
1100000000000000

The MIDR_EL1 can be accessed through the memory-mapped interface and the external debug interface, offset 0xD00.