The MIDR_EL1 characteristics are:
Provides identification information for the processor, including an implementer code for the device and a device ID number.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
The MIDR_EL1 is:
Architecturally mapped to the AArch32 MIDR register. See Main ID Register.
Architecturally mapped to external MIDR_EL1 register.
MIDR_EL1 is a 32-bit register.
Figure 4.1 shows the MIDR_EL1 bit assignments.
Table 4.13 shows the MIDR_EL1 bit assignments.
Indicates the implementer code. This value is:
Indicates the variant number of the processor. This is the major revision number x in the rx part of the rxpy description of the product revision status. This value is:
Indicates the architecture code. This value is:
Indicates the primary part number. This value is:
Indicates the minor revision number of the processor. This is the minor revision number y in the py part of the rxpy description of the product revision status. This value is:
To access the MIDR_EL1:
MRS <Xt>, MIDR_EL1 ; Read MIDR_EL1 into Xt
Table 4.14 shows the register access encoding:
The MIDR_EL1 can be accessed through the memory-mapped interface
and the external debug interface, offset