The MAIR_EL1 characteristics are:
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
MAIR_EL1 is permitted to be cached in a TLB.
MAIR_EL1[31:0] is architecturally mapped to AArch32 register:
MAIR_EL1[63:32] is architecturally mapped to AArch32 register:
MAIR_EL1 is a 64-bit register.
Figure 4.64 shows the MAIR_EL1 bit assignments.
Attr<n> is the memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.
Table 4.105 shows the encoding of bits [7:4] of the Attr<n> field.
|Device memory. See Table 4.106 for the type of Device memory.|
|Normal Memory, Outer Write-through transient.[a]|
|Normal Memory, Outer Non-Cacheable.|
|Normal Memory, Outer Write-back transient.[a]|
|Normal Memory, Outer Write-through non-transient.|
|Normal Memory, Outer Write-back non-transient.|
[a] The transient hint is ignored.
Table 4.106 shows the encoding of bits [0:3] of the Attr<n> field.
|Bits||Meaning when Attr<n>[7:4] is 0000||Meaning when Attr<n>[7:4] is not 0000|
|unpredictable||Normal Memory, Inner Write-through transient|
|Device-nGnRE memory||Normal memory, Inner Non-Cacheable|
|unpredictable||Normal Memory, Inner Write-back transient|
|Device-nGRE memory||Normal Memory, Inner Write-throughnon-transient (RW=00)|
|unpredictable||Normal Memory, Inner Write-through non-transient|
|Device-GRE memory||Normal Memory, Inner Write-back non-transient (RW=00)|
|unpredictable||Normal Memory, Inner Write-back non-transient|
To access the MAIR_EL1:
MRS <Xt>, MAIR_EL1 ; Read EL1 Memory Attribute Indirection Register MSR MAIR_EL1, <Xt> ; Write EL1 Memory Attribute Indirection Register