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4.3.2. Multiprocessor Affinity Register

The MPIDR_EL1 characteristics are:

Purpose

Provides an additional core identification mechanism for scheduling purposes in a cluster system.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

The MPIDR_EL1[31:0] is:

MPIDR_EL1[63:32] is mapped to external EDDEVAFF1 register.

Attributes

MPIDR_EL1 is a 64-bit register.

Figure 4.2 shows the MPIDR_EL1 bit assignments.

Figure 4.2. MPIDR_EL1 bit assignments

Figure 4.2. MPIDR_EL1 bit assignments

Table 4.15 shows the MPIDR_EL1 bit assignments.

Table 4.15. MPIDR_EL1 bit assignments
BitsNameFunction
[63:40]-

Reserved, res0.

[39:32] Aff3

Affinity level 3. Highest level affinity field.

Reserved, res0.

[31]-

Reserved, res1.

[30]U

Indicates a single core system, as distinct from core 0 in a cluster. This value is:

0

Core is part of a cluster.

[29:25]-

Reserved, res0.

[24]MT

Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:

0

Performance of cores at the lowest affinity level is largely independent.

[23:16]Aff2

Affinity level 2. Second highest level affinity field.

Indicates the value read in the CLUSTERIDAFF2 configuration signal.

[15:8]Aff1

Affinity level 1. Third highest level affinity field.

Indicates the value read in the CLUSTERIDAFF1 configuration signal.

[7:0]Aff0

Affinity level 0. Lowest level affinity field.

Indicates the core number in the Cortex-A53 processor. The possible values are:

0x0

A cluster with one core only.

0x0, 0x1

A cluster with two cores.

0x0, 0x1, 0x2

A cluster with three cores.

0x0, 0x1, 0x2, 0x3

A cluster with four cores.


To access the MPIDR_EL1:

MRS <Xt>, MPIDR_EL1 ; Read MPIDR_EL1 into Xt

Register access is encoded as follows:

Table 4.16. MPIDR access encoding
op0op1CRnCRmop2
1100000000000101

The EDDEVAFF0 and EDDEVAFF1 can be accessed through the internal memory-mapped interface and the external debug interface, offsets 0xFA8 and 0xFAC respectively.

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