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4.3.75. Reset Vector Base Address Register, EL3

The RVBAR_EL3 characteristics are:

Purpose

Contains the address that execution starts from after reset when executing in the AArch64 state.

RVBAR_EL3 is part of the Reset management registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RORO
Configurations

There is no configuration information.

Attributes

RVBAR_EL3 is a 64-bit register.

Figure 4.68 shows the RVBAR_EL3 bit assignments.

Figure 4.68. RVBAR_EL3 bit assignments

Figure 4.68. RVBAR_EL3 bit assignments

Table 4.112 shows the RVBAR_EL3 bit assignments.

Table 4.112.  RVBAR_EL3 bit assignments
BitsNameFunction
[63:0]RVBA

Reset Vector Base Address. The address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 0b00, as this address must be aligned, and bits [63:40] are 0x000000 because the address must be within the physical address size supported by the processor.


To access the RVBAR_EL3:

MRS <Xt>, RVBAR_EL3 ; Read RVBAR_EL3 into Xt
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