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4.3.3. Revision ID Register

The REVIDR_EL1 characteristics are:

Purpose

Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

REVIDR_EL1 is architecturally mapped to AArch32 register REVIDR. See Revision ID Register.

Attributes

REVIDR_EL1 is a 32-bit register.

Figure 4.3 shows the REVIDR_EL1 bit assignments.

Figure 4.3. REVIDR_EL1 bit assignments

Figure 4.3. REVIDR_EL1 bit assignments

Table 4.17 shows the REVIDR_EL1 bit assignments.

Table 4.17. REVIDR_EL1 bit assignments
BitsNameFunction
[31:0]ID number

Implementation-specific revision information. The reset value is determined by the specific Cortex-A53 MPCore implementation.

0x00000000

Revision code is zero.


To access the REVIDR_EL1:

MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt

Register access is encoded as follows:

Table 4.18. REVIDR_EL1 access encoding
op0op1CRnCRmop2
1100000000000110

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