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4.3.74. Vector Base Address Register, EL3

The VBAR_EL3 characteristics are:

Purpose

Holds the exception base address for any exception that is taken to EL3.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RWRW
Configurations

The VBAR_EL3[31:0] is mapped to the Secure AArch32 VBAR register. See Vector Base Address Register.

Attributes

VBAR_EL3 is a 64-bit register.

Figure 4.67 shows the VBAR_EL3 bit assignments.

Figure 4.67. VBAR_EL3 bit assignments

Figure 4.67. VBAR_EL3 bit assignments

Table 4.111 shows the VBAR_EL3 bit assignments.

Table 4.111.  VBAR_EL3 bit assignments
BitsNameFunction
[63:11]Vector base address

Base address of the exception vectors for exceptions taken in this exception level.

[10:0]-

Reserved, res0.


To access the VBAR_EL3:

MRS <Xt>, VBAR_EL3 ; Read EL3 Vector Base Address Register
MSR VBAR_EL3, <Xt> ; Write EL3 Vector Base Address Register
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