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4.2.9. AArch64 GIC system registers

Table 4.9 shows the GIC system registers in AArch64 state. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.9. GIC system registers
ICC_AP0R0_EL1RW0x0000000032Active Priorities 0 Register 0
ICC_AP1R0_EL1RW0x0000000032Active Priorities 1 Register 0
ICC_ASGI1R_EL1WO-64Alternate SGI Generation Register 1
ICC_BPR0_EL1RW0x0000000232Binary Point Register 0
ICC_BPR1_EL1RW0x00000003[a]32Binary Point Register 1
ICC_CTLR_EL1RW0x0000040032Interrupt Control Register for EL1
ICC_CTLR_EL3RW0x0000040032Interrupt Control Register for EL3
ICC_DIR_EL1WO-32Deactivate Interrupt Register
ICC_EOIR0_EL1WO-32End Of Interrupt Register 0
ICC_EOIR1_EL1WO-32End Of Interrupt Register 1
ICC_HPPIR0_EL1RO-32Highest Priority Pending Interrupt Register 0
ICC_HPPIR1_EL1RO-32Highest Priority Pending Interrupt Register 1
ICC_IAR0_EL1RO-32Interrupt Acknowledge Register 0
ICC_IAR1_EL1RO-32Interrupt Acknowledge Register 1
ICC_IGRPEN0_EL1RW0x0000000032Interrupt Group Enable Register 0
ICC_IGRPEN1_EL1RW0x0000000032Interrupt Group Enable Register 1
ICC_IGRPEN1_EL3RW0x0000000032Interrupt Group Enable Register 1 for EL3
ICC_PMR_EL1RW0x0000000032Priority Mask Register
ICC_RPR_EL1RO-32Running Priority Register
ICC_SEIEN_EL1RW0x0000000032System Error Interrupt Enable Register
ICC_SGI0R_EL1WO-64SGI Generation Register 0
ICC_SGI1R_EL1WO-64SGI Generation Register 1
ICC_SRE_EL1RW0x0000000032System Register Enable Register for EL1
ICC_SRE_EL2RW0x0000000032System Register Enable Register for EL2
ICC_SRE_EL3RW0x0000000032System Register Enable Register for EL3

[a] This is the reset value in non-secure states. In secure states, the reset value is 0x00000002.