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4.2.1. AArch64 identification registers

Table 4.1 shows the identification registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.1.

Table 4.1. AArch64 identification registers
NameTypeResetWidthDescription
MIDR_EL1RO0x410FD03232

Main ID Register, EL1

MPIDR_EL1RO-[a]64

Multiprocessor Affinity Register

REVIDR_EL1RO0x0000000032

Revision ID Register

ID_PFR0_EL1RO0x0000013132

AArch32 Processor Feature Register 0

ID_PFR1_EL1RO0x10011011[b]32

AArch32 Processor Feature Register 1

ID_DFR0_EL1RO0x0301006632

AArch32 Debug Feature Register 0

ID_AFR0_EL1RO0x0000000032AArch32 Auxiliary Feature Register 0
ID_MMFR0_EL1RO0x1010110532

AArch32 Memory Model Feature Register 0

ID_MMFR1_EL1RO0x4000000032

AArch32 Memory Model Feature Register 1

ID_MMFR2_EL1RO0x0126000032

AArch32 Memory Model Feature Register 2

ID_MMFR3_EL1RO0x0210221132

AArch32 Memory Model Feature Register 3

ID_ISAR0_EL1RO0x0210111032

AArch32 Instruction Set Attribute Register 0

ID_ISAR1_EL1RO0x1311211132

AArch32 Instruction Set Attribute Register 1

ID_ISAR2_EL1RO0x2123204232

AArch32 Instruction Set Attribute Register 2

ID_ISAR3_EL1RO0x0111213132

AArch32 Instruction Set Attribute Register 3

ID_ISAR4_EL1RO0x0001114232

AArch32 Instruction Set Attribute Register 4

ID_ISAR5_EL1RO0x00011121[c]32

AArch32 Instruction Set Attribute Register 5

ID_AA64PFR0_EL1RO0x01002222[d][e]64AArch64 Processor Feature Register 0
ID_AA64PFR1_EL1RO0x00000000

64

AArch64 Processor Feature Register 1
ID_AA64DFR0_EL1RO0x1030510664AArch64 Debug Feature Register 0, EL1
ID_AA64DFR1_EL1RO0x0000000064AArch64 Debug Feature Register 1
ID_AA64AFR0_EL1RO0x0000000064AArch64 Auxiliary Feature Register 0
ID_AA64AFR1_EL1RO0x0000000064AArch64 Auxiliary Feature Register 1
ID_AA64ISAR0_EL1RO

0x00011120[f]

64AArch64 Instruction Set Attribute Register 0, EL1
ID_AA64ISAR1_EL1RO0x0000000064AArch64 Instruction Set Attribute Register 1
ID_AA64MMFR0_EL1RO

0x00001122

64AArch64 Memory Model Feature Register 0, EL1
ID_AA64MMFR1_EL1RO0x0000000064AArch64 Memory Model Feature Register 1
CCSIDR_EL1RO-[g]32

Cache Size ID Register

CLIDR_EL1RO0x0A200023[h]32

Cache Level ID Register

AIDR_EL1RO0x0000000032

Auxiliary ID Register

CSSELR_EL1RW0x0000000032Cache Size Selection Register
CTR_EL0RO0x8444800432Cache Type Register
DCZID_EL0RO

0x00000004

32Data Cache Zero ID Register
VPIDR_EL2RW0x410FD03232

Virtualization Processor ID Register

VMPIDR_EL2RO-[i]64Virtualization Multiprocessor ID Register

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

[b] Bits [31:28] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[c] ID_ISAR5_EL1 has the value 0x00010001 if the Cryptography Extension is not implemented and enabled.

[d] Bits [27:24] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[e] Bits [23:16] are 0x00 if the Advanced SIMD and Floating-point Extension is implemented, and 0xFF otherwise.

[f] ID_AA64ISAR0_EL1 has the value 0x00010000 if the Cryptography Extension is not implemented and enabled.

[g] The reset value depends on the implementation. See the register description for details.

[h] The value is 0x09200003 if the L2 cache is not implemented.

[i] The reset value is the value of the Multiprocessor Affinity Register.


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