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4.2.12. AArch64 implementation defined registers

Table 4.11 shows the implementation defined registers in AArch64 state. These registers provide test features and any required configuration options specific to the Cortex-A53 processor. If a register is not indicated as mapped to an AArch32 64-bit register, bits[63:32] are 0x00000000.

Table 4.11. AArch64 implementation defined registers
NameTypeResetWidthDescription
ACTLR_EL1RW0x0000000032

Auxiliary Control Register, EL1

ACTLR_EL2RW0x0000000032Auxiliary Control Register, EL2
ACTLR_EL3RW0x0000000032Auxiliary Control Register, EL3
AFSR0_EL1RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL1RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
AFSR0_EL2RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL2RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
AFSR0_EL3RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL3RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
AMAIR_EL1RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
AMAIR_EL2RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
AMAIR_EL3RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
L2CTLR_EL1RW-[a]32

L2 Control Register

L2ECTLR_EL1RW0x0000000032

L2 Extended Control Register

L2ACTLR_EL1RW0x80000000[b]32

L2 Auxiliary Control Register

CPUACTLR_EL1[c]RW0x0000 0000 004C800064CPU Auxiliary Control Register, EL1
CPUECTLR_EL1[c]RW0x0000 0000 0000 000064CPU Extended Control Register, EL1
CPUMERRSR_EL1[c]RW-64CPU Memory Error Syndrome Register
L2MERRSR_EL1[c]RW-64L2 Memory Error Syndrome Register
CBAR_EL1RO-[d]64

Configuration Base Address Register, EL1

[a] The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.

[b] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x 80004008.

[c] Mapped to a 64-bit AArch32 register.

[d] The reset value depends on the PERIPHBASE signal.


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