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4.2.7. AArch64 secure registers

Table 4.7 shows the secure registers in AArch64 state.

Table 4.7. AArch64 security registers
NameTypeResetWidthDescription
SCR_EL3RW0x0000000032

Secure Configuration Register

SDER32_EL3RW0x0000000032

Secure Debug Enable Register

CPTR_EL3RW0x00000000[a]32Architectural Feature Trap Register, EL3
MDCR_EL3RW0x0000000032

Monitor Debug Configuration Register, EL3

AFSR0_EL3RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL3RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
VBAR_EL3RW0x000000000000000064Vector Base Address Register, EL3

[a] Reset value is 0x00000000 if Advanced SIMD and Floating point are implemented, 0x00000400 otherwise.


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