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4.2.3. AArch64 virtual memory control registers

Table 4.3 shows the virtual memory control registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.3.

Table 4.3. AArch64 virtual memory control registers
NameTypeResetWidthDescription
SCTLR_EL1RW0x00C50838[a]32

System Control Register, EL1

SCTLR_EL2RW0x30C50838[b]32System Control Register, EL2
SCTLR_EL3RW0x00C50838 [a]32System Control Register, EL3
TTBR0_EL1RWUNK64

Translation Table Base Register 0, EL1

TTBR1_EL1RWUNK64Translation Table Base Register 1
TCR_EL1RWUNK64Translation Control Register, EL1
TTBR0_EL2RWUNK64Translation Table Base Address Register 0, EL2[c]
TCR_EL2RWUNK32Translation Control Register, EL2
VTTBR_EL2RWUNK64

Virtualization Translation Table Base Address Register, EL2[c]

VTCR_EL2RWUNK32Virtualization Translation Control Register, EL2
TTBR0_EL3RWUNK64Translation Table Base Register 0, EL3
TCR_EL3RWUNK32Translation Control Register, EL3
MAIR_EL1RWUNK64

Memory Attribute Indirection Register, EL1

AMAIR_EL1RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
MAIR_EL2RWUNK64

Memory Attribute Indirection Register, EL2

AMAIR_EL2RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
MAIR_EL3RWUNK64

Memory Attribute Indirection Register, EL3

AMAIR_EL3RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
CONTEXTIDR_EL1RWUNK32

Context ID Register, EL1[c]

[a] The reset value depends on primary inputs CFGTE and CFGEND. Table 4.3 assumes these signals are LOW.

[b] The reset value depends on primary inputs CFGTE, CFGEND and VINITHI. Table 4.3 assumes these signals are LOW.

[c] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.


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