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4.2.8. AArch64 virtualization registers

Table 4.8 shows the virtualization registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.8.

Table 4.8. AArch64 virtualization registers
VPIDR_EL2RW0x410FD03132Virtualization Processor ID Register
VMPIDR_EL2RW-[a]64Virtualization Multiprocessor ID Register

System Control Register, EL2

ACTLR_EL2RW0x0000000032Auxiliary Control Register, EL2
HCR_EL2RW0x0000000064Hypervisor Configuration Register

Hyp Debug Control Register


Architectural Feature Trap Register, EL2

HSTR_EL2RW0x0000000032Hyp System Trap Register

Hyp Auxiliary Configuration Register


Translation Table Base Address Register 0, EL3 [d]

TCR_EL2RWUNK32Translation Control Register, EL2

Virtualization Translation Table Base Address Register, EL2 [d]

VTCR_EL2RWUNK32Virtualization Translation Control Register, EL2
DACR32_EL2RWUNK32Domain Access Control Register
AFSR0_EL2RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL2RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
ESR_EL2RWUNK32Exception Syndrome Register, EL2
FAR_EL2RWUNK64Fault Address Register, EL2

Hypervisor IPA Fault Address Register, EL2


Memory Attribute Indirection Register, EL2

AMAIR_EL2RW0x0000000064Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3

Vector Base Address Register, EL2

[a] The reset value is the value of the Multiprocessor Affinity Register.

[b] The reset value depends on inputs, CFGTE and CFGEND. The value shown assumes these signals are set to LOW.

[c] Reset value is 0x0000BFFF if Advanced SIMD and Floating-point are not implemented.

[d] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.