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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

First release


Table C.2. Differences between Issue A and Issue B

Cluster device shutdown sequence updated

Cluster shutdown mode without system driven L2 flushAll revisions
Revision information updated.Chapter 4 System Controlr0p1
GIC programmers model
ETM register descriptions
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
ID_AA64MMFR0_EL1 description updatedAArch64 Memory Model Feature Register 0, EL1All revisions
ACTLR_EL3 description updated.

Auxiliary Control Register, EL3

All revisions
CPUECTLR_EL1 description updated.CPU Extended Control Register, EL1All revisions
ACTLR description updated.

Auxiliary Control Register

All revisions
Updated Encodings for ACE master interfaceTable 7.6All revisions
Table 7.7
List of ACE transactions updated.ACE transfersAll revisions
Shareability description updatedACP user signalsAll revisions
Table A.29
Table A.32
GIC signal descriptions updatedGeneric Interrupt Controller signalsAll revisions
CPUECTLR bit assignment table updatedTable 4.252All revisions

Table C.3. Differences between Issue B and Issue C
Change Multiprocessor, Processor to Cluster, Core naming conventionThroughout documentAll revisions
Removed reference to T32EE (ThumbEE)ARM architectureAll revisions
Updated notes in descriptions of PCLKENDBG, ATCLKEN and CNTCLKEN signalsClocksAll revisions
Updated list of supported core power statesTable 2.5All revisions
Revision information updated.Chapter 4 System Controlr0p2
GIC programmers model
ETM register descriptions
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Updated some register summary information

AArch64 register summary

AArch32 register summary

All revisions
Updated TTBR1 register description

Translation Table Base Register 1

Translation Table Base Register 1

All revisions
Updated CPUMERRSR_EL1 and CPUMERRSR descriptions

Table 4.123

Table 4.154

Table 4.253

All revisions
Removed DACR from list of c4 registersc4 registersAll revisions
Updated GIC system registers in AArch32 summary tables

Table 4.153

c4 registers

c12 registers

All revisions
Added a new table, AArch64 registers used to access internal memoryTable 6.4All revisions
Updated Return stack predictionsReturn stack predictionsAll revisions
Update list of AArch64 registers used to access internal memoryTable 6.4All revisions
Added a new table, MOESI statesTable 6.8All revisions
Updated ACE transfer informationACE transfersAll revisions
Updated ACE and CHI master interface write issuing capability

Table 7.5

Table 7.11

All revisions
Updated AXI privilege informationAXI privilege informationAll revisions
Register names changed in the ROM table Peripheral Identification Registers summaryTable 11.33All revisions
Updated PMU register summary tableTable 12.9All revisions
Peripheral identification and Component identification register names changed in Memory-mapped PMU register summaryTable 12.15All revisions
Updated ETM exception level informationTable 13.1All revisions
Updated ETM programming diagramFigure 13.2All revisions
Updated ETM register purpose and constraint informationThroughout ETM register descriptionsAll revisions
Updated ETM register descriptions

Table 13.37

Table 13.46

All revisions
Updated TRCITIATBOUTR bit assignmentsIntegration Instruction ATB Out Register All revisions

TRCITIATBOUTR.BYTES description updated

Table 13.55All revisions

TRCDEVAFF0 description updated to match MPIDR

Device Affinity Register 0All revisions
Updated sequence of operations in section 11.10.4 (Changing the authentication signals)Changing the authentication signalsAll revisions

Table C.4. Differences between Issue C and Issue D
Updated descriptions of Memory Attribute Indirection Registers

Memory Attribute Indirection Register, EL1

Memory Attribute Indirection Register, EL2

Memory Attribute Indirection Register, EL3

Memory Attribute Indirection Registers 0 and 1

All revisions
Instruction mnemonic updated64-bit registersAll revisions
Added note to CPUECTLR.SMPEN bit descriptionTable 4.252All revisions
SELx signal reduced from 6 bits to 5 bits

Figure 13.21

Table 13.22

All revisions
Updated number of external inputs to trace unit

Table 13.39

All revisions
Footnote added to SAMMNBASE[39,24] description

Table A.17

All revisions

Table C.5. Differences between Issue D and Issue E
Revision information updated.Throughout documentr0p3
Updated description of power states

Table 2.4

Table 2.5

All revisions
Added cache operations to register summary tables

AArch64 cache maintenance operations

AArch64 TLB maintenance operations

AArch64 address translation operations

AArch64 miscellaneous operations

AArch64 EL2 TLB maintenance operations

c7 System operations

c8 System operations

All revisions
Updated reset value for HCR_EL2Table 4.13All revisions
Updated AArch64 GIC register summary tableTable 4.15All revisions
Removed reference to ICC_SEIEN_EL1 registerTable 4.15All revisions
Updated reset value for CPUACTLR_EL1Table 4.17All revisions
Added CPUACTLR_EL1.ENDCCASCI bit description.CPU Auxiliary Control Register, EL1r0p3
Updated reset value for PMCEID0Table 4.150All revisions
Added ICH_VSEIR to register summary tableTable 4.153All revisions
Updated cross reference to TTBCR(NS) in TCR_EL1 descriptionTranslation Table Base Control RegisterAll revisions
Added CPUACTLR.ENDCCASCI bit description.CPU Auxiliary Control Registerr0p3
Added description of EDRCR registerExternal Debug Reserve Control RegisterAll revisions
Updated CPU 0 debug entry in “Address mapping for APB components” tableTable 11.28All revisions
Updated description of GICCDISABLE signalTable A.4All revisions
Updated description of DBGPWRUPREQ signalTable A.6All revisions