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14.5.2. CTI Integration Mode Control Register

The CTIITCTRL characteristics are:

Purpose

The CTIITCTRL shows that the Cortex-A53 processor does not implement an integration mode.

Usage constraints

The accessibility of CTIITCTRL by condition code is:

Off DLKOSLKEDADSLKDefault
----RO/WIRW

Table 14.4 describes the condition codes.

Configurations

CTIITCTRL is in the Debug power domain.

Attributes

See the register summary in Table 14.3.

Figure 14.3 shows the CTIITCTRL bit assignments.

Figure 14.3. CTIITCTRL bit assignments

Figure 14.3. CTIITCTRL bit assignments

Table 14.7 shows the CTIITCTRL bit assignments.

Table 14.7. CTIITCTRL bit assignments
BitsNameFunction
[31:1]-

Reserved, res0.

[0]IME

Integration mode enable. The possible value is:

0

Normal operation.


CTIITCTRL can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xF00.

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