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14.4. Cross trigger register summary

This section describes the cross trigger registers in the Cortex-A53 processor. These registers are accessed through the internal memory-mapped interface or the external debug interface.

Table 14.3 gives a summary of the Cortex-A53 cross trigger registers. For those registers not described in this chapter, see the ARM^® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Table 14.3. Cross trigger register summary
Offset	Name	Type	Description
`0x000`	CTICONTROL	RW	CTI Control Register
`0x000-0x00C`	-	-	Reserved
`0x010`	CTIINTACK	WO	CTI Output Trigger Acknowledge Register
`0x014`	CTIAPPSET	RW	CTI Application Trigger Set Register
`0x018`	CTIAPPCLEAR	WO	CTI Application Trigger Clear Register
`0x01C`	CTIAPPPULSE	WO	CTI Application Pulse Register
`0x020`	CTIINEN0	RW	CTI Input Trigger to Output Channel Enable Registers
`0x024`	CTIINEN1	RW
`0x028`	CTIINEN2	RW
`0x02C`	CTIINEN3	RW
`0x030`	CTIINEN4	RW
`0x034`	CTIINEN5	RW
`0x038`	CTIINEN6	RW
`0x03C`	CTIINEN7	RW
`0x040-0x09C`	-	-	Reserved
`0x0A0`	CTIOUTEN0	RW	CTI Input Channel to Output Trigger Enable Registers
`0x0A4`	CTIOUTEN1	RW
`0x0A8`	CTIOUTEN2	RW
`0x0AC`	CTIOUTEN3	RW
`0x0B0`	CTIOUTEN4	RW
`0x0B4`	CTIOUTEN5	RW
`0x0B8`	CTIOUTEN6	RW
`0x0BC`	CTIOUTEN7	RW
`0x0C0-0x12C`	-	-	Reserved
`0x130`	CTITRIGINSTATUS	RO	CTI Trigger In Status Register
`0x134`	CTITRIGOUTSTATUS	RO	CTI Trigger Out Status Register
`0x138`	CTICHINSTATUS	RO	CTI Channel In Status Register
`0x13C`	CTICHOUTSTATUS	RO	CTI Channel Out Status Register
`0x140`	CTIGATE	RW	CTI Channel Gate Enable Register
`0x144`	ASICCTL	RW	CTI External Multiplexer Control Register
`0x148-0xF7C`	-	-	Reserved
`0xF00`	CTIITCTRL	RW	CTI Integration Mode Control Register
`0xF04-0xFA4`	-	-	Reserved
`0xFA0`	CTICLAIMSET	RW	CTI Claim Tag Set Register
`0xFA4`	CTICLAIMCLR	RW	CTI Claim Tag Clear Register
`0xFA8`	CTIDEVAFF0	RO	CTI Device Affinity Register 0
`0xFAC`	CTIDEVAFF1	RO	CTI Device Affinity Register 1
`0xFB0`	CTILAR	WO	CTI Lock Access Register
`0xFB4`	CTILSR	RO	CTI Lock Status Register
`0xFB8`	CTIAUTHSTATUS	RO	CTI Authentication Status Register
`0xFBC`	CTIDEVARCH	RO	CTI Device Architecture Register
`0xFC0`	CTIDEVID2	RO	CTI Device ID Register 2
`0xFC4`	CTIDEVID1	RO	CTI Device ID Register 1
`0xFC8`	CTIDEVID	RO	CTI Device Identification Register
`0xFCC`	CTIDEVTYPE	RO	CTI Device Type Register
`0xFD0`	CTIPIDR4	RO	Peripheral Identification Register 4
`0xFD4`	CTIPIDR5	RO	Peripheral Identification Register 5-7
`0xFD8`	CTIPIDR6	RO
`0xFDC`	CTIPIDR7	RO
`0xFE0`	CTIPIDR0	RO	Peripheral Identification Register 0
`0xFE4`	CTIPIDR1	RO	Peripheral Identification Register 1
`0xFE8`	CTIPIDR2	RO	Peripheral Identification Register 2
`0xFEC`	CTIPIDR3	RO	Peripheral Identification Register 3
`0xFF0`	CTICIDR0	RO	Component Identification Register 0
`0xFF4`	CTICIDR1	RO	Component Identification Register 1
`0xFF8`	CTICIDR2	RO	Component Identification Register 2
`0xFFC`	CTICIDR3	RO	Component Identification Register 3

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14.4. Cross trigger register summary

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