The processor supports an Accelerator Coherency Port (ACP). This is an AMBA 4 AXI slave interface. The ACP is provided to reduce software cache maintenance operations when sharing memory regions with other masters, and to allow other masters to allocate data into the L2 cache.
The ACP slave interface can receive coherent requests from an external master, but it cannot propagate coherent requests from the Cortex-A53 processor.
See ACP and the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite for more information.