The processor implements the AMBA 4 ACE or AMBA 5 CHI interface:
ACE is an extension to the AXI protocol and provides the following enhancements:
Support for hardware cache coherency.
Barrier transactions that guarantee transaction ordering.
Distributed virtual memory messaging, enabling management of a virtual memory system across multiple MPCore clusters.
See the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite for more information.
CHI is a protocol that provides an architecture for connecting multiple nodes using a scalable interconnect. The nodes on the interconnect might be cores, clusters, I/O bridges, memory controllers, or graphics processors.
See the ARM® AMBA® 5 CHI Protocol Specification.