The GIC CPU Interface, when integrated with an external distributor component, is a resource for supporting and managing interrupts in a cluster system. It provides:
Registers for managing:
Interrupt routing to one or more cores.
The Cortex-A53 processor implements the GIC CPU interface as described in the Generic Interrupt Controller (GICv4) architecture. This interfaces with an external GICv3 or GICv4 interrupt distributor component within the system.
The GICv4 architecture supports:
Two security states.
Software-generated Interrupts (SGIs).
Message Based Interrupts.
System register access.
Memory-mapped register access.
Interrupt masking and prioritization.
Cluster environments, including systems that contain more than eight cores.
Wake-up events in power management environments.
The GIC includes interrupt grouping functionality that supports:
Signaling interrupt groups to the target core using either the IRQ or the FIQ exception request, based on software configuration.
A unified scheme for handling the priority of Group 0 and Group 1 interrupts.
This chapter describes only features that are specific to the Cortex-A53 processor implementation.