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9.2.2. CPU interface register summary

Each CPU interface block provides the interface for a Cortex-A53 processor that interfaces with a GIC distributor within the system. Each CPU interface provides a programming interface for:

  • Enabling the signaling of interrupt requests by the CPU interface.

  • Acknowledging an interrupt.

  • Indicating completion of the processing of an interrupt.

  • Setting an interrupt priority mask for the processor.

  • Defining the preemption policy for the processor.

  • Determining the highest priority pending interrupt for the processor.

  • Generating SGIs.

For more information on the CPU interface, see the ARM Generic Interrupt Controller Architecture Specification.

Table 9.2 lists the registers for the CPU interface.

All the registers in Table 9.2 are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table 9.2. CPU interface register summary
NameTypeResetDescription
GICC_CTLRRW0x00000000CPU Interface Control Register
GICC_PMRRW0x00000000Interrupt Priority Mask Register
GICC_BPRRW

0x00000002 (S)[a]

0x00000003 (NS)[b]

Binary Point Register
GICC_IARRO-Interrupt Acknowledge Register
GICC_EOIRWO-End Of Interrupt Register
GICC_RPRRO0x000000FFRunning Priority Register
GICC_HPPIRRO0x000003FFHighest Priority Pending Interrupt Register
GICC_ABPRRW0x00000003Aliased Binary Point Register
GICC_AIARRO-

Aliased Interrupt Acknowledge Register

GICC_AEOIRWO-

Aliased End of Interrupt Register

GICC_AHPPIRRO0x000003FF

Aliased Highest Priority Pending Interrupt Register

GICC_APR0RW0x00000000Active Priority Register
GICC_NSAPR0RW0x00000000Non-secure Active Priority Register
GICC_IIDRRO0x0034343BCPU Interface Identification Register
GICC_DIRWO-Deactivate Interrupt Register

[a] S = Secure.

[b] NS = Non-secure.


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