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9.2.6. Virtual CPU interface register summary

The virtual CPU interface forwards virtual interrupts to a connected Cortex-A53 processor, subject to the normal GIC handling and prioritization rules. The virtual interface control registers control virtual CPU interface operation, and in particular, the virtual CPU interface uses the contents of the List registers to determine when to signal virtual interrupts. When a core accesses the virtual CPU interface, the List registers are updated. For more information on the virtual CPU interface, see the ARM® Generic Interrupt Controller Architecture Specification.

Table 9.7 describes the registers for the virtual CPU interface.

All the registers in Table 9.7 are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table 9.7. Virtual CPU interface register summary
GICV_CTLRRW0x00000000VM Control Register
GICV_PMRRW0x00000000VM Priority Mask Register
GICV_BPRRW0x00000002VM Binary Point Register
GICV_IARRO-VM Interrupt Acknowledge Register
GICV_EOIRWO-VM End Of Interrupt Register
GICV_RPRRO0x000000FFVM Running Priority Register
GICV_HPPIRRO0x000003FFVM Highest Priority Pending Interrupt Register
GICV_ABPRRW0x00000003VM Aliased Binary Point Register
GICV_AIARRO-VM Aliased Interrupt Acknowledge Register
GICV_AEOIRWO-VM Aliased End of Interrupt Register
GICV_AHPPIRRO0x000003FFVM Aliased Highest Priority Pending Interrupt Register
GICV_APR0RW0x00000000VM Active Priority Register
GICV_IIDRRO0x0034343BVM CPU Interface Identification Register
GICV_DIRWO-VM Deactivate Interrupt Register

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