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9.2.4. Virtual interface control register summary

The virtual interface control registers are management registers. Configuration software on the Cortex-A53 processor must ensure they are accessible only by a hypervisor, or similar software.

Table 9.5 describes the registers for the virtual interface control registers.

All the registers in Table 9.5 are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table 9.5. Virtual interface control register summary
GICH_HCRRW0x00000000Hypervisor Control Register
GICH_VTRRO0x90000003VGIC Type Register

Virtual Machine Control Register


Maintenance Interrupt Status Register


End of Interrupt Status Registers


Empty List Register Status Registers

GICH_APR0RW0x00000000Active Priorities Register
GICH_LR0RW0x00000000List Register 0
GICH_LR1RW0x00000000List Register 1
GICH_LR2RW0x00000000List Register 2
GICH_LR3RW0x00000000List Register 3

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