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1.3. Features

The Cortex-A53 processor includes the following features:

  • Full implementation of the ARMv8-A architecture instruction set with the architecture options listed in ARM architecture.

  • In-order pipeline with symmetric dual-issue of most instructions.

  • Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU).

  • Level 2 (L2) memory system providing cluster memory coherency, optionally including an L2 cache.

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