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5.1. About the MMU

The Cortex-A53 processor is an ARMv8 compliant processor that supports execution in both the AArch64 and AArch32 states. In AArch32 state, the ARMv8 address translation system resembles the ARMv7 address translation system with LPAE and Virtualization Extensions. In AArch64 state, the ARMv8 address translation system resembles an extension to the Long Descriptor Format address translation system to support the expanded virtual and physical address spaces. For more information regarding the address translation formats, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. Key differences between the AArch64 and AArch32 address translation systems are that the AArch64 state provides:

  • A translation granule of 4KB or 64KB. In AArch32, the translation granule is limited to be 4KB.

  • A 16-bit ASID. In AArch32, the ASID is limited to an 8-bit value.

The maximum supported physical address size is 40 bits.

You can enable or disable each stage of the address translation, independently.

The MMU controls table walk hardware that accesses translation tables in main memory. The MMU translates virtual addresses to physical addresses. The MMU provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in page tables. These are loaded into the Translation Lookaside Buffer (TLB) when a location is accessed.

The MMU in each core features the following:

  • 10-entry fully-associative instruction micro TLB.

  • 10-entry fully-associative data micro TLB.

  • 4-way set-associative 512-entry unified main TLB.

  • 4-way set-associative 64-entry walk cache.

  • 4-way set-associative 64-entry IPA cache.

  • The TLB entries include global and application specific identifiers to prevent context switch TLB flushes.

  • Virtual Machine Identifier (VMID) to prevent TLB flushes on virtual machine switches by the hypervisor.

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