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12.6.3. Performance Monitors Common Event Identification Register 1

The PMCEID1 characteristics are:

Purpose

Defines which common architectural and common microarchitectural feature events are implemented.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

ConfigConfigRORORORORO

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1

Configurations

The PMCEID1 is architecturally mapped to:

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

PMCEID1 is a 32-bit register.

Figure 12.7 shows the PMCEID1 bit assignments

Figure 12.7. PMCEID1 bit assignments

Figure 12.7. PMCEID1 bit assignments

Table 12.13 shows the PMCEID1 bit assignments.

Table 12.13. PMCEID1 bit assignments
BitsNameFunction
[31:1]- 
[32]CE[32]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in Table 12.14, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.


Table 12.14. PMU common events
BitEvent numberEvent mnemonicDescription
[0]0x20

L2D_CACHE_ALLOCATE

0

This event is not implemented.


To access the PMCEID1:

MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt

The PMCEID1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE24.

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