The DFAR characteristics are:
Holds the virtual address of the faulting address that caused a synchronous Data Abort exception.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
DFAR(S) - - - RW - - RW DFAR(NS) - - RW - RW RW -
DFAR (NS) is architecturally mapped to AArch64 register FAR_EL1[31:0]. See Fault Address Register, EL1.
DFAR (S) is architecturally mapped to AArch32 register HDFAR. See Hyp Data Fault Address Register.
DFAR (S) is architecturally mapped to AArch64 register FAR_EL2[31:0]. See Fault Address Register, EL2.
DFAR is a 32-bit register.
Figure 4.126 shows the DFAR bit assignments.
Table 4.231 shows the DFAR bit assignments.
The Virtual Address of faulting address of synchronous Data Abort exception
To access the DFAR:
MRC p15, 0, <Rt>, c6, c0, 0 ; Read DFAR into Rt MCR p15, 0, <Rt>, c6, c0, 0 ; Write Rt to DFAR