The ID_ISAR0 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. See:
ID_ISAR0 is architecturally mapped to AArch64 register ID_ISAR0_EL1. See AArch32 Instruction Set Attribute Register 0.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR0 is a 32-bit register.
Figure 4.86 shows the ID_ISAR0 bit assignments.
Table 4.175 shows the ID_ISAR0 bit assignments.
Indicates the implemented Divide instructions:
Indicates the implemented Debug instructions:
Indicates the implemented Coprocessor instructions:
Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:
Indicates the implemented bit field instructions:
Indicates the implemented Bit Counting instructions:
Indicates the implemented Swap instructions in the A32 instruction set:
To access the ID_ISAR0:
MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt
Register access is encoded as follows: