The ID_ISAR1 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See:
ID_ISAR1 is architecturally mapped to AArch64 register ID_ISAR1_EL1. See AArch32 Instruction Set Attribute Register 1.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR1 is a 32-bit register.
Figure 4.87 shows the ID_ISAR1 bit assignments.
Table 4.177 shows the ID_ISAR1 bit assignments.
Indicates the implemented Jazelle state instructions:
Indicates the implemented Interworking instructions:
Indicates the implemented data-processing instructions with long immediates:
Indicates the implemented
Indicates the implemented Extend instructions:
Indicates the implemented A profile exception-handling instructions:
Indicates the implemented exception-handling instructions in the A32 instruction set:
Indicates the implemented Endian instructions:
To access the ID_ISAR1:
MRC p15, 0, <Rt>, c0, c2, 1 ; Read ID_ISAR1 into Rt
Register access is encoded as follows: